Digital Designer FPGA & Video Rendering
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Job Location:
Eindhoven - Netherlands
Monthly Salary:
Not Disclosed
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
About SeeCubic
SeeCubic is working on something most people have never seen before. We develop autostereoscopic 3D display technology that allows viewers to see multidimensional images on TV tablet PC or phone without glasses or any other peripherals. Our technology goes beyond anything previously achieved in 3D visualisation both in precision and detail. From our R&D centre in Eindhoven a team of around 20 engineers works on the software hardware and optics that make this possible.
We are looking for a Digital Designer to design implement and validate video rendering and related features on FPGA using primarily High-Level Synthesis (HLS).
What will you do
You will work on the full cycle of development from requirements gathering and design through to simulation verification and documentation translating complex video processing challenges into robust efficient solutions.
In practice this means:
- Developing IP blocks using High-Level Synthesis (HLS)
- Designing new video processing solutions to improve rendering performance
- Working across all stages of development: requirements design implementation simulation and verification
- Assessing trade-offs in implementation choices such as area power timing and more
- Writing and maintaining technical documentation
- Leveraging AI tools as part of your daily workflow
- Collaborating with external partners in electronics design and manufacturing
You will work closely with electrical engineers and software/embedded engineers reporting directly to the Director of Engineering.
What do you bring
- A degree in Electrical Engineering Computer Science or similar
- 3 or more years of industry experience in video processing with FPGA
- Experience with HLS tools (Catapult HLS is preferred) but Vitis HDL Coder or other tools are accepted
- Experience with pipelining techniques in digital design
- Experience in timing closure analysis and multi-clock domain designs
- TCL scripting for tools such as Quartus or Vivado
- Knowledge of on-chip and off-chip protocols (e.g. AXI-4 Avalon SPI I²C) is a plus
- Experience with AI tools in digital design is a plus
What do we offer
- A permanent contract
- A yearly salary between 45k - 70k depending on education and experience
- 26 vacation days with the option to purchase additional days
- Pension fully covered by the employer. No personal contribution required
- Ample opportunities for training development and personal growth
Interested
Send your CV and a brief motivation to Any questions Feel free to reach out.
Required Experience:
Manager
