Qualifications:
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelors Degree in Electrical/Electronic Engineering or ComputerEngineering or any STEM related education with at least 4 years of relevant experience -OR-Masters Degree in Electrical/Electronic Engineering or Computer Engineering or any STEM relatededucation with at least 3 years of relevant experience.
2 years of experience in digital logic design including instruction set execution ALUs control unitsregisters memory and system buses.
2 years of experience in developing UVM-based testbenches for reusable and scalable verificationenvironments.
2 years of experience in at least one scripting language (e.g. Python Perl or Tcl) C and SystemVerilog.
Preferred Qualifications
Experience with RTL development
Use of AI agents in Verification
Proficiency with C/C System Verilog coding and debug
Knowledge and experience with x86 or any other computer architectures
Familiarity with version control software (GIT).
Experience with Synopsys simulators
Required Skills:
CPU logic designsRTL designersALUsUVM-based testbenchesMasters Degree in Electrical/Electronic EngineeringPytonPerlC
Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimu...
Qualifications:
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelors Degree in Electrical/Electronic Engineering or ComputerEngineering or any STEM related education with at least 4 years of relevant experience -OR-Masters Degree in Electrical/Electronic Engineering or Computer Engineering or any STEM relatededucation with at least 3 years of relevant experience.
2 years of experience in digital logic design including instruction set execution ALUs control unitsregisters memory and system buses.
2 years of experience in developing UVM-based testbenches for reusable and scalable verificationenvironments.
2 years of experience in at least one scripting language (e.g. Python Perl or Tcl) C and SystemVerilog.
Preferred Qualifications
Experience with RTL development
Use of AI agents in Verification
Proficiency with C/C System Verilog coding and debug
Knowledge and experience with x86 or any other computer architectures
Familiarity with version control software (GIT).
Experience with Synopsys simulators
Required Skills:
CPU logic designsRTL designersALUsUVM-based testbenchesMasters Degree in Electrical/Electronic EngineeringPytonPerlC
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