Principal Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence inspiring the world to learn communicate and advance faster than ever.

Lead floor-planning process with emphasis on placement routing optimization PDN planning distribution and TSV placement. Execute APR layout to ensure efficient component placement and routing. Optimize design rules for cost performance and functionality. Collaborate with Architecture Process Integration CAD Probe and Assembly teams to define and implement design methodologies and flows. Conduct timing analysis and power analysis to meet performance and reliability requirements. Analyze power networks to identify and mitigate IR drop and electromigration issues. Perform layout verification tasks including LVS DRC and Antenna checks. Conduct quality checks and maintain documentation. Demonstrate leadership in planning area/time estimation scheduling delegation and execution to meet project milestones. Verify power networks using TOTEM at post-layout for compliance with design specifications and reliability standards. Lead reticle experiments and manage tape-out revisions. Participate in design reviews and provide feedback to improve design quality. Debug and resolve physical design issues in collaboration with engineering teams. Provide experienced technical knowledge to advance innovative solutions. Advise senior management on significant technical issues.

Employer will accept a Bachelors degree in Electrical Engineering Electronic Engineering or related field followed by 8 years of progressive post-baccalaureate experience in job offered or in an Engineering-related occupation.

Position requires:

1. CMOS process experience in analog layout fundamentals including Matching Electro-migration Latch-up coupling cross-talk IR-drop active and passive parasitic devices;
2. Layout skills using Cadence Virtuoso and Cadence Virtuoso XL;
3. Layout methodology from initial chip plan to tapeout;
4. Calibre layout verification tools;
5. ASIC style design flows including floorplanning synthesis place/route layout verification static timing analysis formal/layout verification - flows/processes;
6. Cadence layout tools including Innovus or Tempus or Synopsys including ICC2 or PrimeTime;
7. PDN design and evaluation using tools including TOTEM RedHawk or BSEE.

As a world leader in the semiconductor industry Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well provide peace of mind and help you prepare for the future. We offer a choice of medical dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury and paid family leave. Additionally Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available please see the Benefits Guide posted on is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation age national origin citizenship status disability protected veteran status gender identity or any other factor protected by applicable federal state or local laws.

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