Key Responsibilities
TheOnsiteProjectEngineer role has the main responsibilityto lead end-to-end semiconductor design programs across IP/SoC development. The candidate will bea part of the team which handlescomplex VLSI projectswith a strictschedule scope and quality targets.
Handson Knowledgeon Physical aware synthesis
Develop and Maintain Script flow and scripts
Good knowledge on Constraints development
Optimizedesigns for power performance and area (PPA)
Generate and review reports (timing area powerQoR)
Support low-power implementation (UPF/CPF based flows)
Handson knowledgePre and Post layout Timing analysis forMulti-Mode
Experience on Logix equivalence check using Industry standard tools like Formality and Conformal
Knowledge of DFT modes ispreferable.
Hands on Physical design activities like floorplanning powerplanning CTS Routing
MandatorySkills
Over5years of hands-on experience in semiconductor (SoC) development projectsforVLSI/ASIC/SoC domain
Strong understanding of full chip design lifecycle:
ArchitectureRTLVerificationSynthesisP&RSignoffTapeout
Practical experience in RTL development verification or physical design
SoundUnderstanding of semiconductor development processes (Lint/CDC/STA/DFT/P&R etc.)
Strong knowledge of semiconductor processes (7nm/5nm/advanced nodes preferred)
Exposure toIP integration or full-chip SoC programs
Experience of working inday-do-day communicationMS-Officetools such MS WordPowerPoint Excel MS teams
Exposure tocollaborating withmulti-site / offshore teams
More than 5 years of projectexecutionexperience (schedule quality risk management)
Bilingual Business levelJapanese Englishproficiency(capable of technical discussions viapresentationsmeetingsandemailcommunication)
Soft Skills:
Ability to organize information andprovideclear guidance in technology projects with manyuncertainties
Abilityto work in fast-paced deadline-driven environments
Strong communicationskills to build trust in collaboration with multicultural teams
Ability to solve problems involving multiple domains through cause analysis and logical approaches
Excellent stakeholder management & communication skills
Strong leadership and mentoringabilityProblem-solvingand decision-making skills
DesiredExperience:
Experience in advanced nodes (7nm / 5nm / below)
Exposure to low-power design techniques
Exposure to UPF
Experience in high-frequency designs (>1GHz)
Knowledge of DFT integration
Experience in SoC-level synthesis
Educational Qualifications:
Bachelors/masters degree in Electrical/Electronics/InstrumentationEngineering
Required Experience:
Senior IC
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