Senior Digital Verification Engineer

Lead ASIC Verification Engineer

(Typically 6 to 10 years of industry experience)

The Digital Engineering group is a highly collaborative organization comprising experienced ASIC and Systems engineers with deep expertise across architecture logic design verification physical design hardwaresoftware cosimulation FPGA prototyping and firmware development. The team brings together decades of cumulative industry experience and operates at the forefront of modern semiconductor design.

We leverage advanced semiconductor process technologies and industrystandard stateoftheart EDA tools to deliver highquality silicon solutions. Our scope spans the full SoC development lifecycle from architectural definition through verification validation and final product delivery.

Responsibilities

• Implement and execute verification for IP blocks and subsystems using SystemVerilog and UVM following established verification methodologies and plans.
• Develop and enhance UVM components including agents monitors drivers scoreboards assertions and functional coverage models.
• Author and execute test plans and testcases including directed and constrainedrandom tests to validate functional correctness and corner cases.
• Contribute to verification closure analyzing coverage results identifying gaps and adding tests or coverage points to meet signoff requirements.
• Participate in lowpower verification assisting with UPF/CPF integration and validating powerrelated scenarios under guidance.
• Assist in HWFW coverification including development and execution of C/C tests for simulation or prototyping platforms.
• Debug RTL issues collaborating with design engineers to resolve functional mismatches assertion failures and coverage holes.
• Execute and maintain regressions triaging failures and ensuring stability of the verification environment.
• Review specifications and design documents raising questions and identifying potential verification risks early in the development cycle.
• Work closely with peers and senior engineers contribute to team deliverables and continuously improving verification quality.

Qualifications / Skills

• Handson experience in ASIC/IP verification with at least one or more tapeout cycles in a professional semiconductor environment.
• Good proficiency in SystemVerilog and UVM with experience developing test benches and testcases.
• Working knowledge of core verification concepts including:
  • Test planning and execution
  • Directed and constrainedrandom stimulus
  • Functional and code coverage
  • Basic assertionbased verification
  • Introduction to lowpower verification concepts
• Exposure to C/C programming for verification or HWFW interaction.
• Basic scripting skills (Python Perl or similar) for automation and debug support.
• Experience using version control and issuetracking tools such as Git and Jira.
• Strong problemsolving skills attention to detail and willingness to learn with the ability to take ownership of assigned verification tasks.
• Effective written and verbal communication skills and ability to work well within a team environment.

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