Lead ASIC Physical Design Engineer

San Diego, CA - USA

Monthly Salary: Not Disclosed

Posted on: 3 hours ago

Vacancies: 1 Vacancy

Job Summary

Job Function:

ASIC Physical Design implementation using IC Compiler; Logic Synthesis I/O Pad Ring Design Floor Planning Placement CTS Routing STA with Timing Closure in Advanced Technology closure methodology implementation and sign off Power grid Clock tree and Low-power reduction Implementation methods; Signal integrity fixes with OCV/AOCV/Statistical Timing methods Physical Verification Conformal Equivalence Check Conformal Lower Power (CLP) IR drop analysis PERL TCL Scripting for all ASIC Methodology Implementations

Tools:

PrimeTime SI PrimeTime PX Design Compiler Topographical Synopsys Formality RedHawk

Qualification Requirements :

Minimum Education : Bachelors deegree in Electrical Engineering
Minimum experience: Five (5) years
Position requires five (5) years of post-baccalaureate experience that is progressive in nature
Five (5) years of experience must include five (5) years of experience in: PrimeTime SI PrimeTime PX Design Compiler Topographical Synopsys Formality RedHawk

Job Function: ASIC Physical Design implementation using IC Compiler; Logic Synthesis I/O Pad Ring Design Floor Planning Placement CTS Routing STA with Timing Closure in Advanced Technology closure methodology implementation and sign off Power grid Clock tree and Low-power reduction Implementation m...