Resolution Enhancement Techniques Technologist

About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the worlds brightest minds TI creates innovations that shape the future of technology. TI is helping about 100000 customers transform the future today. Were committed to building a better future from the responsible manufacturing of our semiconductors to caring for our employees to giving back inside our communities and developing great minds. Put your talent to work with us change the world love your job!

About the job

As a Resolution Enhancement Techniques (RET) Technologist youll architect new TI products and make our customers visions a reality. Youll define design model implement and document analog digital and RF integrated circuits (ICs). Responsibilities will include but are not limited to:

• Partnering with design process engineering and process integration teams to develop mutually agreeable design specifications for manufacturing processes for advanced analog nodes.
• Developing/improving mask/lithography/etch processes for next node analog nodes through photolithographic simulation and on mask/wafer verification.
• Data collection simulation and verification of optical proximity correction (OPC) models and recipes.
• Partnering with internal/external fabs to transfer processes for advanced nodes.
• Troubleshooting photolithographic patterning/alignment related issues for all fabs within TI.

The person performing this role must be capable to plan effectively drive schedules meet critical deadlines on multiple tasks in parallel lead technical discussions in their area of expertise and work effectively across organizational boundaries. They must be able to clearly communicate project status and actions. Additionally they must be able to interface with multiple organizations and work well on a diverse team to accomplish goals.

Minimum requirements:

• PhD in Electrical Engineering Physics Computer Science Chemistry or related degree.
• 15 years experience in a semiconductor photolithography and/or OPC development.
• Lithography & RET expertise for 45nm 28nm 22nm and 20nm processing nodes.
• Knowledge of critical care-abouts for 28 nm node processing.
• Expertise in double patterning schemes and test structure requirements to validate OPC solutions.
• Ability to lead and drive advanced processes associated with double patterning techniques in 20 nm node development.
• Strong knowledge/understanding of advanced lithography processes lithography simulation techniques mask making and RET techniques used in semiconductor manufacturing and process development.

Preferred qualifications:

• Familiarity with physical layout (gds/oas).
• Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software like Virtuoso KLayout.
• Programming experience in Unix environment.
• Understanding of OPC pattern validation methodologies and process window assessment techniques like KLAs Photolithography Wafer Qualification (PWQ).
• Demonstrated strong analytical and problem solving skills.
• Strong verbal and written communication skills.
• Ability to work in teams and collaborate effectively with people in different functions.
• Strong time management skills that enable on-time project delivery.
• Demonstrated ability to build strong influential relationships.
• Ability to work effectively in a fast-paced and rapidly changing environment.
• Ability to take the initiative and drive for results.