Overview:
TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and project management
Position: RTL Design Engineer
Location: Bangalore
Work Type: Onsite
Job Type: Full time
Job Description:
- Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SV is mandatory (Pls note - we DO NOT want RTL INTEGRATION engineer profiles here)
- Experience in converting Micro-architecture to synthesizable RTL code keeping in mind area latency and power constraints is needed
- Experience in running QC checks (CDC Lint X-prop) on the design and cleaning up design issues is mandatory
- FPGA RTL projects/profiles will be discounted from total experience/rejected
- Synthesis and constraint writing experience is good to have but not mandatory
Skills Required:
Experience Required:
TekWissen Group is an equal opportunity employer supporting workforce diversity.
Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and ...
Overview:
TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and project management
Position: RTL Design Engineer
Location: Bangalore
Work Type: Onsite
Job Type: Full time
Job Description:
- Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SV is mandatory (Pls note - we DO NOT want RTL INTEGRATION engineer profiles here)
- Experience in converting Micro-architecture to synthesizable RTL code keeping in mind area latency and power constraints is needed
- Experience in running QC checks (CDC Lint X-prop) on the design and cleaning up design issues is mandatory
- FPGA RTL projects/profiles will be discounted from total experience/rejected
- Synthesis and constraint writing experience is good to have but not mandatory
Skills Required:
Experience Required:
TekWissen Group is an equal opportunity employer supporting workforce diversity.
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