About the team:
Our team deliver many high-performance products based on the industrys most advanced technology with high frequencies up to product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm the team you will face great challenges such as FP CTS STA etc. At the same time you will get rich experience and advanced methodology.
Job Responsibilities:
Focus on high-speed digital DDR PHY IP physical implementation develop necessary scripts or tools to enhance current PD design flow. Work in product projects including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results implement optimal design parameters and flows for different projects.
Job Requirement:
-BS with minimum 4 years of experience. MS with minimum 2 years of experience.
-Good physical design experience in the digital implementation domain including Floorplan CTS STA Physical verification Power analysis.
-Solid background in circuits electronics physics be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language such as Perl C shell TCL Makefile Python.
-Familiar with EDA tools like Innovus ICC Calibre Tempus PrimeTime etc.
Required Experience:
IC
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