Analog Mixed Signal Layout Engineer
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Monthly Salary:
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
About the company
Empower Semiconductor based in Silicon Valley powers the AI revolution with its FinFast technology by reducing the energy footprint and total cost of ownership of data centers. Its transformational integrated voltage regulators deliver on-demand scalable power with the speed precision and signal integrity required by AI processors. Empowers power-management architecture shrinks solution footprint height and component count achieving vertical power delivery with unprecedented power density and efficiency. Learn more follow us on LinkedIn.
Role Overview
To expand the team in Munich we are seeking an experienced Analog/Mixed-Signallayout Engineer to contribute to the development of high-performance power management ICs in advanced CMOS this role you will collaborate closely with circuit designers to deliver high-density ultra efficient layout implementations that meet aggressive performance and size targets.
The ideal candidate has 10 years of hands-on experience in Analog/Mixed-Signal IC layout (or 5 years experience in Power IC layout) deep expertise in custom analog layout and thrives in a startup-like high-accountability culture.
Key Responsibilities
- Execute full-custom layout of analog/mixed-signal building blocks including LDOs bandgaps opamps comparators and switching regulators (DC/DC) in planar and FinFET technologies.
- Macro-IP-level floorplan and layout implementation of large analog/mixed-signal blocks with attention to matching shielding routing symmetry parasitic electromigration DFM area optimization.
- Support concept layout (ahead of project kick-off) including comparison of area performance and mask count of different technologies.
- Drive lead and execute layout (including Tape-Out procedures and GDS submission) of test-vehicles i.e. technology characterization test-structures/wafers (i.e. Fab Shuttles).
- Perform physical verification: DRC LVS ERC using industry standard tools.
- Collaborate with designers to iterate and optimize layouts based on circuit sensitivities and extracted simulation results.
- Ensure reliability and manufacturability through proper layout practices.
- Macro-IP-level planning: create effort estimates create and maintain layout execution plan track layout tasks progress take preventive and corrective actions to ensure Macro-IP execution runs according to plan.
- If required coordinate layout task with junior colleagues or external sub-cons: distribute monitor review improve quality of layout.
Qualifications:
- BS or MS in Electrical Engineering with 5 years experience in Power IC layout or 10 years in Analog/Mixed-Signal IC layout.
- Expert-level proficiency with Cadence Virtuoso and verification tools.
- Strong understanding of analog layout techniques: device matching noise isolation current density and thermal awareness.
- Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment.
- Experience with FinFet layout is highly desirable.
- Experience with hands-on parasitic analysis post-layout circuit simulation and parasitic optimization is desirable.
- Good communication skills (verbal written).
Required Experience:
IC
Key Skills
- Design Engineering
- Design
- Engineering
- Design Management
- Control System
About Company
We Minimize the Energy Footprint of the Digital Economy. Best-in-class regulators deliver highest power density and performance with fewer components.
