Formal Verification Engineer

Markham - Canada

Monthly Salary: Not Disclosed

Posted on: 3 hours ago

Vacancies: 1 Vacancy

Job Summary

Overview:

TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.

Position: Formal Verification Engineer

Location: Markham ON

Duration: 9 Months

Job Type: Temporary Assignment

Work Type: Hybrid

Job Description:

The GMHUB team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in.
We are currently looking for an experienced ASIC Design Verification engineer who will be involved in different aspects of verification activities with focus being formal verification.
The candidate will manage/utilize a variety of verification components methodologies (formal/simulation) to ensure the robustness of RTL designs.
This role offers you the chance to work with some of the most talented verification experts in the industry applying cutting-edge verification techniques to verify our complex designs.

The Person:

You have a passion for modern complex digital design and verification in general.
You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills attention to detail and willing to learn and ready to take on problems.

Responsibilities:

Drive formal verification execution with support from FV and design leads.
Collaborate with design and architecture teams to understand design specifications and develop verification requirements
Debug testbench and/or design issues using formal tools and provide feedback for design improvements
Responsible for verification quality metrics like pass rates code/functional coverage and proof convergence
Document Formal Verification processes.
Continuously learn and stay ahead of the curve in verification in general and formal in particular.

Preferred experience:

Successful candidate should possess the following personal qualities and technical skills:

Experience with System Verilog Assertions SystemVerilog / Verilog is a must
Strong understanding OOP and UVM is a huge asset.
Experience with Low Power Verification and debug methodology is a plus
VCS/DVE familiarity is necessary and experience with formal tools like VC-Formal/Jasper is a huge plus.
Knowledge of scripting languages like Python and Tcl is plus.

Top 3-5 must have skills:

Experience with System Verilog Assertions SystemVerilog / Verilog
VCS/DVE familiarity is necessary and experience with formal tools like VC-Formal/Jasper
Test plan execution development and debug testbench and/or design issues using formal tools and provide feedback for design improvements
Knowledge of scripting languages like Python and Tcl

TekWissen Group is an equal opportunity employer supporting workforce diversity.

Overview: TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processo...