Principal Engineer, HSIO Digital Design

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Advancing the Worlds Technology Together

Our technology solutions power the tools you use every day--including smartphones electric vehicles hyperscale data centers IoT devices and so much more. Here youll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of whats possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. Were dedicated to empowering people to be their true selves. Together were building a better tomorrow for our employees customers partners and communities.

Samsung Semiconductor Inc. (SSI) is advancing the worlds technology. As a leader in Memory System LSI and LCD technologies our US teams contribute to breakthroughs in 5G SOC memory and display. With our global perspective and diversity of thought we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Location: Daily onsite presence at our San Jose CA headquarters in alignment with our Flexible Work policy.

What Youll Do

This team is focused on next-generation HSIO (High-Speed I/O) design for Samsungs AI production platforms. Ideal candidates will have 10 years of industry experience specializing in digital design for die-to-die(chiplet) interfaces or similar high-speed I/O technologies.

Candidates are expected to have a strong understanding of the end-to-end digital design flow and the ability to collaborate effectively with system and analog teams.

What You Bring

• BS degree with 20 years MS degree with 18 years or PhD with 15 years of experience in High-Speed I/O design
• Hands-on experience with Die-to-Die interface IP (e.g. UCIe BOW) including:
• RTL design and verification
• Logic synthesis and Static timing analysis (STA)
• Semi-custom physical design
• Silicon validation and SoC integration
• Deep understanding of high-speed serial interconnect architectures (e.g. UCIe PCIe 100G/200G Ethernet) and associated design trade-offs
• Strong understanding of how analog and mixed-signal design and verification impact digital-on-top development flows
• Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs
• Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link
• Knowledge of Design for Testability (DFT) methodologies and flows
• Familiarity with Ethernet PMA / PMD / PCS layers
• Experience with firmware development for embedded microcontroller systems.
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

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Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel regardless of race religion color age disability sex gender identity sexual orientation ancestry genetic information marital status national origin political affiliation or veteran status.

When selecting team members we prioritize talent and qualities such as humility kindness and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities long-term conditions neurodivergent individuals or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

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