Overview:
TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and project management
Position: Senior/Principal ASIC Design Verification Engineer (SoC/Subsystem)
Location: Bangalore
Work Type: Onsite
Job Type: Full time
Job Description:
- Lead SoC Verification Engineer (UVM / TB Architecture)
Role summary
- Own end-to-end verification of complex SoCs or large subsystems. This is a hands-on role from testbench architecture to coverage closure through tapeout and into silicon correlation.
What youll do
- Architect and build scalable UVM testbenches from scratch at subsystem or SoC level
- Strong hands-on experience in testbench development
- Define verification strategy and author test plans from specs and micro-architecture
- Develop constrained-random and directed tests scoreboards checkers assertions (SVA) and coverage models
- Drive functional code and assertion coverage closure with discipline
- Debug complex issues using waveforms logs and root-cause analysis
- Lead SoC-level verification: IP integration coherency low-power modes resets/boot and performance validation
- Work closely with RTL architecture DFT and firmware teams
- Support silicon bring-up and pre-/post-silicon correlation
Must-have skills:
- 8 years of hands-on ASIC verification (FPGA/emulation-only experience does not count)
- Strong TB Architecture ownership - design reuse strategy scalability and maintainability
- Multiple production ASIC tapeouts with SoC or large subsystem ownership
- Expert in SystemVerilog UVM SVA and constrained-random methodologies
- Deep experience with AXI/ACE DDR PCIe coherency memory and interrupt fabrics
- Proven strength in test planning stimulus strategy checkers/scoreboards and closure execution
- Excellent debug skills across simulation and silicon correlation
TekWissen Group is an equal opportunity employer supporting workforce diversity.
Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and ...
Overview:
TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and project management
Position: Senior/Principal ASIC Design Verification Engineer (SoC/Subsystem)
Location: Bangalore
Work Type: Onsite
Job Type: Full time
Job Description:
- Lead SoC Verification Engineer (UVM / TB Architecture)
Role summary
- Own end-to-end verification of complex SoCs or large subsystems. This is a hands-on role from testbench architecture to coverage closure through tapeout and into silicon correlation.
What youll do
- Architect and build scalable UVM testbenches from scratch at subsystem or SoC level
- Strong hands-on experience in testbench development
- Define verification strategy and author test plans from specs and micro-architecture
- Develop constrained-random and directed tests scoreboards checkers assertions (SVA) and coverage models
- Drive functional code and assertion coverage closure with discipline
- Debug complex issues using waveforms logs and root-cause analysis
- Lead SoC-level verification: IP integration coherency low-power modes resets/boot and performance validation
- Work closely with RTL architecture DFT and firmware teams
- Support silicon bring-up and pre-/post-silicon correlation
Must-have skills:
- 8 years of hands-on ASIC verification (FPGA/emulation-only experience does not count)
- Strong TB Architecture ownership - design reuse strategy scalability and maintainability
- Multiple production ASIC tapeouts with SoC or large subsystem ownership
- Expert in SystemVerilog UVM SVA and constrained-random methodologies
- Deep experience with AXI/ACE DDR PCIe coherency memory and interrupt fabrics
- Proven strength in test planning stimulus strategy checkers/scoreboards and closure execution
- Excellent debug skills across simulation and silicon correlation
TekWissen Group is an equal opportunity employer supporting workforce diversity.
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