Were Hiring: Digital Front-End Lead (8-15 Years Experience)
Work Mode: On-Premises
Willware Technologies is looking for an experienced and passionate Digital Front-End Lead to drive chip-level architecture RTL design and verification efforts while leading a high-performing engineering team.
We are seeking a Verification Leader with design exposure capable of influencing architecture ensuring robust verification strategies and driving continuous improvement.
What Were Looking For
Top Priority Skills (Level 5)
Chip-Level Verification
-
Use-case understanding
-
Verification planning & reviews
-
Stimulus specification & verification item extraction
-
Dynamic & static verification environments
-
Gate-level simulation with back-annotated delays
Leadership & Management
-
Team management (DFE team)
-
Project planning
-
Collaboration with backend & analog teams
-
Documentation & continuous improvement
-
Exposure to functional safety standards
High Priority Skills (Level 4)
RTL Design & Quality Verification
-
RTL coding (Verilog / SystemVerilog)
-
RTL quality checks using EDA tools
-
RTL quality control & validation
Core Technical Skills (Level 3)
-
Chip-level architecture & microarchitecture design
-
Constraint creation & synthesis (SDC/STA)
-
Chip-level assembly using EDA tools
-
Multi-power domain design & power system modeling
-
Testing support: SCAN BIST cutout tests
-
On-board evaluation & mass production support
Additional Skills (Level 2)
Additional Notes
Target products are not FPGA-based
Experience with MCU products featuring ARM cores is preferred
Required Skills:
PROJECT PLANNINGTESTING
Were Hiring: Digital Front-End Lead (8-15 Years Experience) Work Mode: On-Premises Willware Technologies is looking for an experienced and passionate Digital Front-End Lead to drive chip-level architecture RTL design and verification efforts while leading a high-performing engineering team. We are...
Were Hiring: Digital Front-End Lead (8-15 Years Experience)
Work Mode: On-Premises
Willware Technologies is looking for an experienced and passionate Digital Front-End Lead to drive chip-level architecture RTL design and verification efforts while leading a high-performing engineering team.
We are seeking a Verification Leader with design exposure capable of influencing architecture ensuring robust verification strategies and driving continuous improvement.
What Were Looking For
Top Priority Skills (Level 5)
Chip-Level Verification
-
Use-case understanding
-
Verification planning & reviews
-
Stimulus specification & verification item extraction
-
Dynamic & static verification environments
-
Gate-level simulation with back-annotated delays
Leadership & Management
-
Team management (DFE team)
-
Project planning
-
Collaboration with backend & analog teams
-
Documentation & continuous improvement
-
Exposure to functional safety standards
High Priority Skills (Level 4)
RTL Design & Quality Verification
-
RTL coding (Verilog / SystemVerilog)
-
RTL quality checks using EDA tools
-
RTL quality control & validation
Core Technical Skills (Level 3)
-
Chip-level architecture & microarchitecture design
-
Constraint creation & synthesis (SDC/STA)
-
Chip-level assembly using EDA tools
-
Multi-power domain design & power system modeling
-
Testing support: SCAN BIST cutout tests
-
On-board evaluation & mass production support
Additional Skills (Level 2)
Additional Notes
Target products are not FPGA-based
Experience with MCU products featuring ARM cores is preferred
Required Skills:
PROJECT PLANNINGTESTING
View more
View less