Intern, CPU Design Engineer

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Our technology solutions power the tools you use every day--including smartphones electric vehicles hyperscale data centers IoT devices and so much more. Here youll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of whats possible and powering the future.

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What Youll Learn

• Project Overview: High Performance RISC-V OoO Superscalar CPU
• Skills Youll Learn:
  
  • Define microarchitecture of feature(s) or extensions for RISC-V CPU Write and test RTL for the features and integrate in the CPU
  • Hands-on experience in cutting-edge CPU design projects.
    

What Youll Do

The Architecture Research Lab (ARL) is one of the research teams of Samsung Advanced Institute of Technology (SAIT) which is Samsungs R&D hub established as the incubator for cutting-edge technologies. SAITs mission has covered various research areas from AI applications/algorithms research neuromorphic processor domain-specific accelerators to new materials quantum computing and super computer system.

ARL is committed to shaping the future of CPU processor and SoC architecture for the most demanding applications of the future like AI and HPC. We are building the foundation of processors and the related platform which are applied to various business targets of Samsung in the future.

We are seeking a highly motivated intern to join our CPU Design and Micro-Architecture team in Summer 2026. As an intern you will have the opportunity to work alongside experienced engineers to contribute to the design development and verification of CPU microarchitectures. You will assist in the design and implementation of key components of modern processors including pipeline stages memory hierarchy and communication protocols gaining hands-on experience in cutting-edge CPU technologies.

Location: Daily onsite presence at our San Jose CA headquarters in alignment with our Flexible Work policy

Reports to: Sr. Staff Engineer ASIC Design

Req ID: 42715

• Assist in the design and development of CPU microarchitecture components such as pipelines execution units and caches.
• Collaborate with senior engineers on micro-architectural modeling and analysis to improve performance power and area efficiency.
• Help in the development of RTL designs for various CPU blocks and contribute to verification and validation efforts.
• Participate in architecture definition discussions and assist in performance analysis using simulators and tools.
• Debug and resolve design issues using simulation and hardware emulation environments.
• Document design work test plans and test cases as part of the project deliverables.
• Complete other responsibilities as assigned.

What You Bring

• Currently pursuing Masters or PhD degree in Electrical Engineering Computer Engineering or related field.
• Must have at least 1 academic quarter/semester remaining
• Strong understanding coursework or experience in digital logic design computer architecture microprocessor design and parallel programming etc. concepts
• Familiarity with HDL languages such as Verilog SystemVerilog and VHDL.
• Strong knowledge of CPU pipeline architecture instruction sets (RISC-V ARM x86) and memory hierarchy.
• Experience with simulation and verification tools (e.g. VCS Verdi ModelSim Questa or equivalent) and FPGA tools- Vivado or Quartus- is a plus.
• Exposure to RISC-V or other instruction set architectures.
• Experience with FPGA development or CPU emulation environments.
• Knowledge of scripting languages (e.g. Perl TCL Python) for automation preferred.
  
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

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Experience:

Intern