Senior Staff FPGAFirmware Design Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Architect and develop FPGA logic.
• Integrate common code blocks into designs.
• Simulate FPGA design solutions.
• Achieve timing closure on FPGA designs.
• Validate FPGA designs.
• Debug board problems with a focus on FPGA debug levels.
• Collaborate with internal firmware/software teams on implementing system level diagnostics.
• Bring up and test prototypes.
• Develop and implement test plans.
• Perform and lead Lab debug of HW/FPGA problems.
• Contribute to formal design processes including requirements management and documentation.

What Were Looking For

• Bachelor CE/EE degree (MS preferred) in ElectricalEngineering with 5years of experienceindata communication systems or similar field.
• Proficiency in FPGA architecture design modelling simulation and verification.
• Expertise in Verilog.
• System Verilog a plus and VHDL a plus.
• Proficiency with FPGA design tools such as Vivado.
• Experience with Simulation/Verification tools.
• Experience with serial I2C/I3C/SPI/MDIO/PMBUS/etc communication bus.
• Experience with parallel interface (APB AXI).
• Strong knowledge and application of high-speed design methodologies for FPGA logic.
• Solid understanding of digital design principles and synchronous design techniques.
• Experience with Logic level interface of service processors.
• Proficient in the complete flow of CAD design tools such as Cadence Concept Allegro.
• Proficient in constraint driven design methodologies.
• Working knowledge of circuit design and layout techniques including analog digital programmable logic and microcontroller technologies.
• Strong working knowledge of Windows environment and scripting using shell scripts TCL Python etc.
• Experience working as a team with other FPGA designers.
• Excellent communication and leadership skills.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.