PCB Layout Engineer

Chandler, TX - USA

Monthly Salary: Not Disclosed

Posted on: 08-11-2025

Vacancies: 1 Vacancy

Job Summary

PCB Layout Engineer for Compute and High-Speed Interfaces

Role:

We require an experienced Senior PCB Layout Engineer (>10yrs) of developing complex high-speed multi-layer HDI layouts to support Clients Hardware Platforms team.
Participate in early-stage PCB route studies and layout feasibility for our hardware development platforms used to evaluate Clients custom system-on-chip (SoC) and reference designs.
The team is working at the forefront of embedded compute focusing on prototyping Clients latest IP products.

Responsibilities:

Collaborate with hardware designers and packaging engineers to support early-stage feasibility studies from footprint creation component placement to fanout and route studies of high-speed parallel and serial busses optimising for signal integrity power integrity layer count and cost.
You will utilise and leverage your skills to design PCBs for complex data centre compute platforms to meet the requirements of the project team and our customers whilst ensuring optimal performance and manufacturability.

Qualifications:

Highly experienced with the layout of PCB platforms for embedded compute.
Experience of designing complex impedance controlled multi-layer (>20) PTH and HDI PCBs with high pin count devices (>8K) high-speed interfaces (PCIe Gen5/6 and LPDDR5/6) differential pairs high-current power planes.
Experience of working alongside a chip packaging team.
Able to influence and advise on pinout and routing topologies of SoCs or complex FPGA devices cost optimisation routing feasibility and layer trade-off analysis.
Detailed knowledge of escape routing of high density SoCs FPGAs able to provide estimates of the IO count that can be routed with a particular stack-up and rule set.
Appreciation of Signal Integrity and Power Integrity as applicable to routing strategies.
Extensive knowledge PCB fabrication of complex multi-layer stack ups (PTH & HDI) IPC standards and substrate materials via structures and design rules.
Proficient in the use of EDA Tools specifically Cadence OrCAD CIS / Allegro PCB suite.
Ability to collaborate with PCB fabricators for DFM/DFT and automated assembly.
Ensure designs are aligned with leading edge suppliers and best practise.
Good interpersonal and communication skills.

Desirable Skills and Qualities

Certified Interconnect Designer (CID CID)
Experience with version control systems (e.g. SVN)
Experience of automating: decoupling capacitor optimisation IC placement optimisation drawing templates etc.

PCB Layout Engineer for Compute and High-Speed Interfaces Role: We require an experienced Senior PCB Layout Engineer (>10yrs) of developing complex high-speed multi-layer HDI layouts to support Clients Hardware Platforms team. Participate in early-stage PCB route studies and layout feasibility f...

PCB Layout Engineer for Compute and High-Speed Interfaces

Role:

We require an experienced Senior PCB Layout Engineer (>10yrs) of developing complex high-speed multi-layer HDI layouts to support Clients Hardware Platforms team.
Participate in early-stage PCB route studies and layout feasibility for our hardware development platforms used to evaluate Clients custom system-on-chip (SoC) and reference designs.
The team is working at the forefront of embedded compute focusing on prototyping Clients latest IP products.

Responsibilities:

Collaborate with hardware designers and packaging engineers to support early-stage feasibility studies from footprint creation component placement to fanout and route studies of high-speed parallel and serial busses optimising for signal integrity power integrity layer count and cost.
You will utilise and leverage your skills to design PCBs for complex data centre compute platforms to meet the requirements of the project team and our customers whilst ensuring optimal performance and manufacturability.

Qualifications:

Highly experienced with the layout of PCB platforms for embedded compute.
Experience of designing complex impedance controlled multi-layer (>20) PTH and HDI PCBs with high pin count devices (>8K) high-speed interfaces (PCIe Gen5/6 and LPDDR5/6) differential pairs high-current power planes.
Experience of working alongside a chip packaging team.
Able to influence and advise on pinout and routing topologies of SoCs or complex FPGA devices cost optimisation routing feasibility and layer trade-off analysis.
Detailed knowledge of escape routing of high density SoCs FPGAs able to provide estimates of the IO count that can be routed with a particular stack-up and rule set.
Appreciation of Signal Integrity and Power Integrity as applicable to routing strategies.
Extensive knowledge PCB fabrication of complex multi-layer stack ups (PTH & HDI) IPC standards and substrate materials via structures and design rules.
Proficient in the use of EDA Tools specifically Cadence OrCAD CIS / Allegro PCB suite.
Ability to collaborate with PCB fabricators for DFM/DFT and automated assembly.
Ensure designs are aligned with leading edge suppliers and best practise.
Good interpersonal and communication skills.

Desirable Skills and Qualities

Certified Interconnect Designer (CID CID)
Experience with version control systems (e.g. SVN)
Experience of automating: decoupling capacitor optimisation IC placement optimisation drawing templates etc.