DFT Engineer

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Job Description:

Broadcoms ASIC Product Division is seeking candidates for a DFT position at Shanghai. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)s designs DFT Architecture Test insertion and verification Pattern generation Coverage improvement Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

It is expected that you can code using TCL PERL RUBY PYTHON C or similar.

Responsibilities:

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
• Implementing DFT including Scan MBIST TAP LBIST IO SerDes and other I/P DFT integration
• Working closely with STA and DI Engineers design closure for test
• Generating Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis diagnostics & yield improvement efforts
• Interfacing with the customer physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 7nm & beyond
• Automating DFT & Test Vector Generation flows

• Strong DFT background (such as IO and Analog DFT ATPG and/or Scan BIST and others)
• Scan Insertion and scan compression background (DFT Compiler Mentor TestKompress etc.)
• Well-versed in ATPG vector generation simulation and debugging. (TetraMax Fastscan)
• Experience in Verilog coding testbench generation & simulation
• Memory BIST insertion and verification experience on embedded (SRAM CAM eDRAM ROM)
• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
• Basic knowledge Test-STA and constraints
• Strong background on IEE1687 IJTAG ICL and PDL
• The ability to work in a multi-disciplined cross-department environment
• Solid knowledge in analog and digital circuit design and device physics fundamentals
• Good understanding of Si processing logical and physical synthesis and transistor reliability principles
• Excellent problem solving debug root cause analysis and communication skills
• Experience working on the ATE is a plus
• Experience with Serdes DDR PCIE ENET CXL IOBIST verification and silicon debug is a plus
• Experience working on Tessent SSN is a plus

Education & Experience:

• Bachelors in Electrical/Electronic/Computer Engineering and 10 years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 8 years of relevant industry experience

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race color creed religion sex sexual orientation national origin citizenship disability status medical condition pregnancy protected veteran status or any other characteristic protected by federal state or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA please be sure to fill out a home address as this will be used for future correspondence.