STA (Static Timing Analysis) Engineer Advanced Technologies Group
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Job Location:
Monthly Salary:
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
In this role you will be responsible for developing and owning IP-level Netlist generation (Synthesis UPF scan insertion external IPs integration) & timing constraints for both regular and custom requirements from synthesis to sign-off ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure with the CAD team to understand and develop the flow and with the Physical Design team to finalize and sign off on the timing. Additionally you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
- 5 years of experience in the field
- At least 2 years of experience in writing ASIC timing constraints and achieving timing closure
- Expertise in STA tools (Primetime) and flow generation
- Knowledge of the ASIC design timing closure flow and methodology
- Understanding of timing corners/modes
- Familiarity with process variations and signal integrity-related issues
- Hands-on experience in generating and managing timing/SDC constraints proficient in scripting languages (Tcl and Perl)
- Knowledge of synthesis DFT and backend-related methodologies and tools
- Strong communication skills are required as you will interact with various groups
Key Skills
- Anti Money Laundering
- Internship
- Consultancy
- Information Technology Sales
- Accident Investigation
- ASP
About Company
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