PI design guidelines aligned with system
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Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
Job Title:Signal Integrity (SI) & Power Integrity (PI) Engineer
Onsite - San Jose CA
Experience:5 Years
Work Mode:Onsite / Work from Office
Role Overview:
We are seeking aSignal Integrity Engineerto supporthigh-speed interface development and validation. Youll work on cutting-edge technologies such asLPDDR5X PCIe Gen7 and UCIe (64G) collaborating closely with design package and PCB teams to ensure top performance.
Responsibilities:
Performchannel modeling extractions and eye analysisfor high-speed interfaces.
Conductpre- and post-layout simulationsto ensure standard compliance.
Analyzecrosstalk reflections jitter insertion/return loss.
Executepower integrity extractions and simulationsfor high-speed interfaces.
Model and analyzepackage/board PDN definedecoupling strategy and validate performance.
Collaborate across teams tooptimize SI/PI performance.
Generatetechnical reports and recommendationsfor design decisions.
ProvideSI/PI design guidelinesaligned with system requirements.
Qualifications:
BE/MTechinElectronics & CommunicationorElectrical & Electronics.
Strong background inSignal & Power Integrity.
Hands-on withSI toolsandPI extraction/simulation tools(e.g. PowerSI SIwave AEDT HSPICE or equivalent).
In-depth knowledge ofDDR PCIe UCIe standardsandPDN design best practices.
Familiar withJEDEC LPDDR5/6 andPCIe/UCIestandards.
Excellentanalytical problem-solving and communicationskills.
Onsite - San Jose CA
Experience:5 Years
Work Mode:Onsite / Work from Office
Role Overview:
We are seeking aSignal Integrity Engineerto supporthigh-speed interface development and validation. Youll work on cutting-edge technologies such asLPDDR5X PCIe Gen7 and UCIe (64G) collaborating closely with design package and PCB teams to ensure top performance.
Responsibilities:
Performchannel modeling extractions and eye analysisfor high-speed interfaces.
Conductpre- and post-layout simulationsto ensure standard compliance.
Analyzecrosstalk reflections jitter insertion/return loss.
Executepower integrity extractions and simulationsfor high-speed interfaces.
Model and analyzepackage/board PDN definedecoupling strategy and validate performance.
Collaborate across teams tooptimize SI/PI performance.
Generatetechnical reports and recommendationsfor design decisions.
ProvideSI/PI design guidelinesaligned with system requirements.
Qualifications:
BE/MTechinElectronics & CommunicationorElectrical & Electronics.
Strong background inSignal & Power Integrity.
Hands-on withSI toolsandPI extraction/simulation tools(e.g. PowerSI SIwave AEDT HSPICE or equivalent).
In-depth knowledge ofDDR PCIe UCIe standardsandPDN design best practices.
Familiar withJEDEC LPDDR5/6 andPCIe/UCIestandards.
Excellentanalytical problem-solving and communicationskills.
Required Skills:
HSPICE
Job Title:Signal Integrity (SI) & Power Integrity (PI) Engineer
Onsite - San Jose CA
Experience:5 Years
Work Mode:Onsite / Work from Office
Role Overview:
We are seeking aSignal Integrity Engineerto supporthigh-speed interface development and validation. Youll work on cutting-edge technologies such asLPDDR5X PCIe Gen7 and UCIe (64G) collaborating closely with design package and PCB teams to ensure top performance.
Responsibilities:
Performchannel modeling extractions and eye analysisfor high-speed interfaces.
Conductpre- and post-layout simulationsto ensure standard compliance.
Analyzecrosstalk reflections jitter insertion/return loss.
Executepower integrity extractions and simulationsfor high-speed interfaces.
Model and analyzepackage/board PDN definedecoupling strategy and validate performance.
Collaborate across teams tooptimize SI/PI performance.
Generatetechnical reports and recommendationsfor design decisions.
ProvideSI/PI design guidelinesaligned with system requirements.
Qualifications:
BE/MTechinElectronics & CommunicationorElectrical & Electronics.
Strong background inSignal & Power Integrity.
Hands-on withSI toolsandPI extraction/simulation tools(e.g. PowerSI SIwave AEDT HSPICE or equivalent).
In-depth knowledge ofDDR PCIe UCIe standardsandPDN design best practices.
Familiar withJEDEC LPDDR5/6 andPCIe/UCIestandards.
Excellentanalytical problem-solving and communicationskills.
Onsite - San Jose CA
Experience:5 Years
Work Mode:Onsite / Work from Office
Role Overview:
We are seeking aSignal Integrity Engineerto supporthigh-speed interface development and validation. Youll work on cutting-edge technologies such asLPDDR5X PCIe Gen7 and UCIe (64G) collaborating closely with design package and PCB teams to ensure top performance.
Responsibilities:
Performchannel modeling extractions and eye analysisfor high-speed interfaces.
Conductpre- and post-layout simulationsto ensure standard compliance.
Analyzecrosstalk reflections jitter insertion/return loss.
Executepower integrity extractions and simulationsfor high-speed interfaces.
Model and analyzepackage/board PDN definedecoupling strategy and validate performance.
Collaborate across teams tooptimize SI/PI performance.
Generatetechnical reports and recommendationsfor design decisions.
ProvideSI/PI design guidelinesaligned with system requirements.
Qualifications:
BE/MTechinElectronics & CommunicationorElectrical & Electronics.
Strong background inSignal & Power Integrity.
Hands-on withSI toolsandPI extraction/simulation tools(e.g. PowerSI SIwave AEDT HSPICE or equivalent).
In-depth knowledge ofDDR PCIe UCIe standardsandPDN design best practices.
Familiar withJEDEC LPDDR5/6 andPCIe/UCIestandards.
Excellentanalytical problem-solving and communicationskills.
Required Skills:
HSPICE
Key Skills
- Anti Money Laundering
- Actuarial
- Cafe
- Council
- Fabrication
- Bid Management
