As a CPU Microarchitect/RTL Engineer you will own or participate in the following: Micro-architecture development and specification - from early high-level architectural exploration through micro-architectural research and arriving at a detailed specification RTL ownership - development assessment and refinement of RTL design to target power performance area and timing goals Verification - support the verification team in test bench development formal methods and simulation/emulation for functional verification Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing area reliability testability and power
- Minimum BS and 10 years of relevant industry experience
- Experience with microprocessor architecture
- Experience with logic design principles with timing and power implications
- Experience in Verilog or VHDL
- Experience with simulators and waveform debugging process
- Expertise in one or more of the following areas: out-of-order execution instruction scheduling integer and floating point execution load/store execution cache and memory subsystems
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C programming
- Experience using an interpretive language such as Perl or Python
As a CPU Microarchitect/RTL Engineer you will own or participate in the following: Micro-architecture development and specification - from early high-level architectural exploration through micro-architectural research and arriving at a detailed specification RTL ownership - development assessment a...
As a CPU Microarchitect/RTL Engineer you will own or participate in the following: Micro-architecture development and specification - from early high-level architectural exploration through micro-architectural research and arriving at a detailed specification RTL ownership - development assessment and refinement of RTL design to target power performance area and timing goals Verification - support the verification team in test bench development formal methods and simulation/emulation for functional verification Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing area reliability testability and power
- Minimum BS and 10 years of relevant industry experience
- Experience with microprocessor architecture
- Experience with logic design principles with timing and power implications
- Experience in Verilog or VHDL
- Experience with simulators and waveform debugging process
- Expertise in one or more of the following areas: out-of-order execution instruction scheduling integer and floating point execution load/store execution cache and memory subsystems
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C programming
- Experience using an interpretive language such as Perl or Python
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