A successful candidate will be responsible for designing implementing testing and operating a complex real-time software system that runs on a globally-distributed heterogeneous compute platform and processes every bit of information exchanged to realize the satellite connectivity.
- 10 years of experience of designing and implementing high-bandwidth data-processing application on Xilinx FPGA / SoC platforms in System Verilog or HLS.
- 5 years of experience of designing FPGA accelerators in HLS (Xilinx Vitis HLS).
- 5 years of experience of workflow automation data analysis and data visualization in Python.
- Ability to design the CPU-FPGA interface based on the standard protocols (AXI-MM AXI-Stream) and the standard Linux subsystems (contiguous memory allocation user I/O device tree).
- Ability to set up a Yocto Linux or Petalinux project for a custom Xilinx SoC board from scratch.
- Ability to write kernel-space user-space device drivers in C for high-bandwidth and real-time hardware accelerators / custom peripherals.
- Knowledge of and ability to mentor other team members on modern design/coding best practices.
- General radio-frequency (RF) digital signal processing knowledge.
- Hands-on development experience in areas related to 5G WiFi GNSS CCSDS and/or SpaceWire.
Required Experience:
Senior IC
A successful candidate will be responsible for designing implementing testing and operating a complex real-time software system that runs on a globally-distributed heterogeneous compute platform and processes every bit of information exchanged to realize the satellite connectivity. 10 years of exper...
A successful candidate will be responsible for designing implementing testing and operating a complex real-time software system that runs on a globally-distributed heterogeneous compute platform and processes every bit of information exchanged to realize the satellite connectivity.
- 10 years of experience of designing and implementing high-bandwidth data-processing application on Xilinx FPGA / SoC platforms in System Verilog or HLS.
- 5 years of experience of designing FPGA accelerators in HLS (Xilinx Vitis HLS).
- 5 years of experience of workflow automation data analysis and data visualization in Python.
- Ability to design the CPU-FPGA interface based on the standard protocols (AXI-MM AXI-Stream) and the standard Linux subsystems (contiguous memory allocation user I/O device tree).
- Ability to set up a Yocto Linux or Petalinux project for a custom Xilinx SoC board from scratch.
- Ability to write kernel-space user-space device drivers in C for high-bandwidth and real-time hardware accelerators / custom peripherals.
- Knowledge of and ability to mentor other team members on modern design/coding best practices.
- General radio-frequency (RF) digital signal processing knowledge.
- Hands-on development experience in areas related to 5G WiFi GNSS CCSDS and/or SpaceWire.
Required Experience:
Senior IC
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