As an ASIC STA Engineer you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners modes and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of sophisticated SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.
- BS and 3 years of relevant industry experience.
- Hands-on experience in ASIC timing constraints generation and timing closure.
- Good knowledge in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV noise and crosstalk effects on timing.
- Good understanding and experience in timing closure of various test modes such as scan shift scan capture atspeed and BIST testing.
- Own STA sign-off for block and chip level including custom timing checks.
- Hands on experience in timing/SDC constraints generation and management.
- Knowledge of low-power techniques including clock gating power gating and multi-voltage designs.
- Proficient in scripting languages (Tcl and Perl/Python).
- Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of different groups (e.g. digital design DFT physical design etc.).
- MS and 3 years of relevant industry experience.
- Strong background in Constraint analysis and debug using industry standard tools such as Synopsys CA (Constraint Analyzer).
- Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.
- Solid understanding of timing corners/modes process variations and signal integrity related issues.
As an ASIC STA Engineer you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across a...
As an ASIC STA Engineer you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners modes and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of sophisticated SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.
- BS and 3 years of relevant industry experience.
- Hands-on experience in ASIC timing constraints generation and timing closure.
- Good knowledge in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV noise and crosstalk effects on timing.
- Good understanding and experience in timing closure of various test modes such as scan shift scan capture atspeed and BIST testing.
- Own STA sign-off for block and chip level including custom timing checks.
- Hands on experience in timing/SDC constraints generation and management.
- Knowledge of low-power techniques including clock gating power gating and multi-voltage designs.
- Proficient in scripting languages (Tcl and Perl/Python).
- Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of different groups (e.g. digital design DFT physical design etc.).
- MS and 3 years of relevant industry experience.
- Strong background in Constraint analysis and debug using industry standard tools such as Synopsys CA (Constraint Analyzer).
- Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.
- Solid understanding of timing corners/modes process variations and signal integrity related issues.
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