Electronic Design Automation (EDA) Technical Architect
(West Coast/California area) - Onsite/Hybrid: Hybrid role (any clients locations)
Contract
Job Description/Specifications
Evaluate the clients current EDA system architecture and identify risks to IP integrity and segregation.
Advise on technical transformation strategies to modernize and optimize EDA workflows.
Benchmark competitor EDA practices and recommend enhancements aligned with industry best practices.
Support integration planning for upcoming acquisition ensuring clean IP boundaries.
Collaborate with engineering and IT teams to implement schematic layout and verification improvements.
Qualifications Proven experience with Cadence and/or Synopsys EDA tools in semiconductor environments.
Strong understanding of VLSI design methodologies and chip lifecycle management.
Expertise in IP protection segregation and compliance within complex system integrations.
Familiarity with key EDA functions: logic synthesis timing analysis place-and-route and physical verification.
Ability to translate technical insights into actionable recommendations for business stakeholders
Electronic Design Automation (EDA) Technical Architect (West Coast/California area) - Onsite/Hybrid: Hybrid role (any clients locations) Contract Job Description/Specifications Evaluate the clients current EDA system architecture and identify risks to IP integrity and segregation. Advise on...
Electronic Design Automation (EDA) Technical Architect
(West Coast/California area) - Onsite/Hybrid: Hybrid role (any clients locations)
Contract
Job Description/Specifications
Evaluate the clients current EDA system architecture and identify risks to IP integrity and segregation.
Advise on technical transformation strategies to modernize and optimize EDA workflows.
Benchmark competitor EDA practices and recommend enhancements aligned with industry best practices.
Support integration planning for upcoming acquisition ensuring clean IP boundaries.
Collaborate with engineering and IT teams to implement schematic layout and verification improvements.
Qualifications Proven experience with Cadence and/or Synopsys EDA tools in semiconductor environments.
Strong understanding of VLSI design methodologies and chip lifecycle management.
Expertise in IP protection segregation and compliance within complex system integrations.
Familiarity with key EDA functions: logic synthesis timing analysis place-and-route and physical verification.
Ability to translate technical insights into actionable recommendations for business stakeholders
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