In this highly visible role you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists designers and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification ensuring the highest design quality.
- Minimum requirement of a bachelors degree.
- Advanced knowledge of Verilog SystemVerilog and UVM.
- Knowledge of SystemVerilog Assertion.
- Knowledge and experience of ASIC verification flows including test bench development constrained random testing and code/functional coverage.
- Proficient in shell and Python scripting Perl scripting.
- Experience of using AI technologies in data mining/analysis.
- Verification experience of one or more of the following a plus: MAC PHY DMA timer AMBA bus and fabric encryption/decryption engine.
- Knowledge of wireless protocols such as Bluetooth UWB WLAN or Zigbee.
- Should be a team player with excellent communication skills self-motivated and well organized.
In this highly visible role you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer you will be responsible for pre-silicon RTL verifica...
In this highly visible role you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists designers and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification ensuring the highest design quality.
- Minimum requirement of a bachelors degree.
- Advanced knowledge of Verilog SystemVerilog and UVM.
- Knowledge of SystemVerilog Assertion.
- Knowledge and experience of ASIC verification flows including test bench development constrained random testing and code/functional coverage.
- Proficient in shell and Python scripting Perl scripting.
- Experience of using AI technologies in data mining/analysis.
- Verification experience of one or more of the following a plus: MAC PHY DMA timer AMBA bus and fabric encryption/decryption engine.
- Knowledge of wireless protocols such as Bluetooth UWB WLAN or Zigbee.
- Should be a team player with excellent communication skills self-motivated and well organized.
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