Physical Design EMIRESD Lead

Job Title: Physical Design EM/IR/ESD Lead

Location: Bengaluru India Experience: 10 15 years Industry: Semiconductors AI Networking ASIC Design

Key Responsibilities: EM/IR/ESD Focus

Methodology & Flow Development

Define & Own EM/IR/ESD Flow: Design develop and maintain a robust automated and scalable physical

design flow specifically for Electromigration (EM) Static and Dynamic IR-Drop (IR) analysis and ESD

Power Distribution Network (PDN) Leadership: Lead the definition of the System-on-Chip (SoC) level

Power Distribution Network (PDN) architecture including on-chip power grid decap strategy and power

delivery methodology. Drive partition-level teams to meet target IR-drop and power integrity specifications.

ESD/LUP Strategy: Collaborate with the SoC integration and floorplanning teams to define and implement

the necessary ESD and Latch-Up protection elements across the chip to meet industry-standard

specifications (e.g. HBM CDM).

Advanced Sign-off Methodology: Proactively develop and implement innovative methodologies to

enhance the accuracy and reduce the Turn-Around-Time for EM/IR and ESD sign-off ensuring silicon

reliability.

Tool Expertise & Vendor Collaboration

Tool Evaluation & Benchmarking: Lead the evaluation selection and deployment of best-in-class EDA

tools for EM/IR analysis (e.g. Ansys RedHawk SC Cadence Voltus) and ESD/LUP sign-off (e.g.

Calibre PERC). Conduct rigorous benchmarking to optimize flow efficiency.

Vendor Engagement: Serve as the primary technical interface with EDA vendors for EM/IR/ESD tools.

Drive feature enhancements debug tool issues and influence product roadmaps to meet the projects

critical reliability and sign-off requirements.

Technical Leadership & Support

Sign-off Expertise: Act as the subject matter expert (SME) for all EM IR-drop and ESD/LUP aspects.

Provide expert-level support on complex sign-off challenges and final tape-out criteria.

Cross-Functional Collaboration: Work closely with the Process Technology/Foundry team to

incorporate technology-specific rules and models for EM/IR into the flow and with the Device/Layout team

to optimize ESD/LUP protection structures.

Key Skills and Qualifications

Essential Expertise

EM/IR Sign-off Mastery: Solid expertise in EM/IR sign-off flows and methodologies for advanced

technology nodes. Proven ability to analyze and debug static/dynamic IR-drop and identify EM violations.

Tool Proficiency: High proficiency with leading EM/IR analysis tools such as Ansys RedHawk SC

and/or Cadence Voltus.

ESD/LUP Sign-off: Mastery of ESD and Latch-Up protection concepts design implications and sign-off

procedures.

Tool Proficiency: Proficiency with Calibre PERC flows to execute analyze results and achieve

tape-out sign-off for ESD/LUP.

Physical Design Fundamentals: Strong understanding of core physical design concepts including

floorplanning power grid mesh creation place-and-route and timing analysis with a specific focus on

how they impact power integrity.

Scripting & Automation: Expert proficiency in scripting languages is essential for flow development and

automation. Must be proficient in Python and/or Perl/TCL.

Background and Experience

Education: Bachelors or Masters degree in Electrical Engineering Electronics or a related field.

Experience: Relevant 10 15 years experience in VLSI physical design with a dedicated focus on EMIR

IR-drop ESD and Latch-Up analysis and methodology.

Process Technology: Proven experience working on advanced process nodes (7nm/5nm and below) is

highly desirable.

Soft Skills

Problem-Solving: Exceptional analytical and debugging skills with a demonstrated ability to solve complex

power and reliability challenges independently.

Communication: Excellent verbal and written communication skills with the ability to effectively drive

technical decisions across cross-functional teams (PD Analog Integration Foundry) and clearly articulate

sign-off status.