Experienced AMS Design Verification Engineer

Apple

Not Interested
Bookmark
Report This Job

profile Job Location:

London - UK

profile Monthly Salary: Not Disclosed
Posted on: 30+ days ago
Vacancies: 1 Vacancy

Job Summary

Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs. The AMS DV engineer goes beyond standard verification techniques and include: - performance-based analysis - power related analysis and scenario design for early power estimation - deliveries of tests for design and test engineering teams- gate-level verification (power and timing) - lab bring-up support A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV teams DNA.


  • Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
  • Hands-on experience with constrained random verification environments
  • Basic design background in support of verification results analysis
  • Knowledge of Object Oriented Programming (OOP)
  • Proficiency in English language is required


  • Masters degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
  • Hands-on experience with Assertion Based Verification
  • Familiarity with system design using C Python or Verilog
  • Familiarity with FPGA emulation platforms
  • Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants including minorities women protected veterans and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about disclose or discuss their compensation or that of other applicants.

Required Experience:

Senior IC

Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs. The AMS DV engineer g...
View more view more

Key Skills

  • Arabic Speaking
  • Logistics Operations
  • Lecturing
  • Community Support
  • Gynaecology & Obstetrics
  • AC Maintenance

About Company

Company Logo

Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more

View Profile View Profile