As a Timing Integration Engineer you will be a key member of the radio team integrating and bringing the next-generation wireless SoCs into high-volume production at sophisticated CMOS technology nodes for Apple products.
- BS and a minimum of 10 years relevant industry experience
- Prior use of analog and digital timing closure tools like NanoTime and PrimeTime to identify relevant timing arcs and verify analog-to-digital signal interface high speed timing.
- Familiarity with custom analog blocks within the radio transceiver such as digital PLLs and RX/TX datapath IPs.
- Experience with Cadence Spectre analog design tools for running analog simulations as needed.
- MSEE with extensive experience for top radio level timing and digital verification.
- Digital Power Analysis tools such as PTPX to help evaluate digital radio blocks power profiles.
- Solid digital background in RTL design synthesis and FE-STA to be able to work with digital teams to architect high speed data paths and DSPs that communicate with RF and analog sub-cells.
- Understanding of ATPG and DFT support for SOC scan debug chains and their timing to the radio sub-cells.
- Analog modeling & netlist verification tools such as Insight Analyzer and SimVision to verify signal integrity and connectivity at the radio level.
As a Timing Integration Engineer you will be a key member of the radio team integrating and bringing the next-generation wireless SoCs into high-volume production at sophisticated CMOS technology nodes for Apple products.BS and a minimum of 10 years relevant industry experiencePrior use of analog an...
As a Timing Integration Engineer you will be a key member of the radio team integrating and bringing the next-generation wireless SoCs into high-volume production at sophisticated CMOS technology nodes for Apple products.
- BS and a minimum of 10 years relevant industry experience
- Prior use of analog and digital timing closure tools like NanoTime and PrimeTime to identify relevant timing arcs and verify analog-to-digital signal interface high speed timing.
- Familiarity with custom analog blocks within the radio transceiver such as digital PLLs and RX/TX datapath IPs.
- Experience with Cadence Spectre analog design tools for running analog simulations as needed.
- MSEE with extensive experience for top radio level timing and digital verification.
- Digital Power Analysis tools such as PTPX to help evaluate digital radio blocks power profiles.
- Solid digital background in RTL design synthesis and FE-STA to be able to work with digital teams to architect high speed data paths and DSPs that communicate with RF and analog sub-cells.
- Understanding of ATPG and DFT support for SOC scan debug chains and their timing to the radio sub-cells.
- Analog modeling & netlist verification tools such as Insight Analyzer and SimVision to verify signal integrity and connectivity at the radio level.
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