As a SOC Integration Engineer you will have responsibilities to design IPs.- Working with other specialists that are members of the SoC Design SoC Design Verification System Verification STA and Physical Design teams to implement designs/flows for sophisticated SOCs.- Integrating various IPs and ensuring design meets DFT (design-for-test) CDC (clock domain crossing) Synthesis/Static Timing and Power Requirements.- Working with CAD and Flow teams to define and improve front-end de sign methodologies.- Developing micro-architecture and design specifications.- Implementing and verifying sophisticated logic designs.- Working with designers on STA physical power and logical issues
- Bachelors Degree 0 Years of Experience
- Deep experience in RTL Logic Design of multi-million gate ASICs.
- Hands on experience for all aspects of the chip development process with proficiency in front end tools and methodologies related to synthesis formal verification CDC analysis ECO and power checks.
- Shown experience writing micro-architecture specifications and converting them to design.
- Experience crafting low power ASICs/SOCs from scratch.
As a SOC Integration Engineer you will have responsibilities to design IPs.- Working with other specialists that are members of the SoC Design SoC Design Verification System Verification STA and Physical Design teams to implement designs/flows for sophisticated SOCs.- Integrating various IPs and e...
As a SOC Integration Engineer you will have responsibilities to design IPs.- Working with other specialists that are members of the SoC Design SoC Design Verification System Verification STA and Physical Design teams to implement designs/flows for sophisticated SOCs.- Integrating various IPs and ensuring design meets DFT (design-for-test) CDC (clock domain crossing) Synthesis/Static Timing and Power Requirements.- Working with CAD and Flow teams to define and improve front-end de sign methodologies.- Developing micro-architecture and design specifications.- Implementing and verifying sophisticated logic designs.- Working with designers on STA physical power and logical issues
- Bachelors Degree 0 Years of Experience
- Deep experience in RTL Logic Design of multi-million gate ASICs.
- Hands on experience for all aspects of the chip development process with proficiency in front end tools and methodologies related to synthesis formal verification CDC analysis ECO and power checks.
- Shown experience writing micro-architecture specifications and converting them to design.
- Experience crafting low power ASICs/SOCs from scratch.
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