Candidates will be responsible for PPA optimisation of the netlist working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration you will deliver the outstanding GPUs for the best consumer products. If youre ready to help chart the future of Apple Silicon we would love to talk to you.
- Familiarity with DFT insertion;
- Familiarity with reset domain multi-clock domain multi-power domain (UPF) linting tools and concepts across RTL and Gate-Level;
- Experience implementing ECOs for functionality and timing.
- Experience with physical synthesis including logic and PPA optimisation techniques.
- Ability to analyze critical paths and guide RTL designs to efficient solutions.
- Experience using logic equivalence tools for RTL and Gate-level designs.
- Collaborate optimally with IP teams spanning multiple sites.
Candidates will be responsible for PPA optimisation of the netlist working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaborat...
Candidates will be responsible for PPA optimisation of the netlist working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration you will deliver the outstanding GPUs for the best consumer products. If youre ready to help chart the future of Apple Silicon we would love to talk to you.
- Familiarity with DFT insertion;
- Familiarity with reset domain multi-clock domain multi-power domain (UPF) linting tools and concepts across RTL and Gate-Level;
- Experience implementing ECOs for functionality and timing.
- Experience with physical synthesis including logic and PPA optimisation techniques.
- Ability to analyze critical paths and guide RTL designs to efficient solutions.
- Experience using logic equivalence tools for RTL and Gate-level designs.
- Collaborate optimally with IP teams spanning multiple sites.
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