Senior Verification Engineers Mixed Signal Verification Engineer

Job Title: Senior Verification Engineers / Mixed Signal Verification Engineer

Location: Austin TX (On-site 5 days a week)
Experience: 6 15 Years
Employment Type: Full-time Onsite Only
Visa Sponsorship: H1-B Sponsorship Available / US Citizens and Green Card Holders only

About the Role

We are seeking talented Senior Verification Engineers and Mixed Signal Verification Engineers to join a well-funded fast-growing semiconductor company developing cutting-edge programmable coherent DSP technologies for next-generation high-speed communication systems. These roles offer an opportunity to work on industry-defining innovations enabling faster more efficient data transmission across AI and cloud infrastructure.

Key Responsibilities

• Plan and perform verification of digital and mixed-signal design blocks per specifications.
• Collaborate closely with RTL and analog design engineers to ensure functionality and performance.
• Build advanced verification environments using SystemVerilog and UVM methodologies.
• Identify and implement comprehensive coverage metrics for all functional and corner cases.
• Perform functional block/cluster testing and debug issues alongside design teams.
• Conduct coverage collection analyze metrics and drive towards verification closure.
• Develop behavioral models (BM) of analog designs for digital verification.
• Use chip-level digital design tools to perform mixed-signal dynamic verification (no AMS simulation).
• Leverage Virtuoso schematic tools for integration and verification activities.
• Prepare detailed verification test plans document results and communicate with cross-functional teams.

Required Qualifications

• 6 years of experience in VLSI design verification or mixed-signal verification.
• Proven track record of completing two or more full block/system verification cycles.
• Deep understanding of VLSI verification flows languages and concepts.
• Strong hands-on experience in SystemVerilog and verification methodologies such as UVM OVM or eRM.
• Experience with data path or communication protocols (Ethernet preferred).
• Proficiency with Verilog/SystemVerilog coding and Virtuoso schematic tools.
• Working knowledge of analog design fundamentals.
• Familiarity with verification methodologies simulators waveform viewers execution automation and coverage tools.

Preferred Qualifications

• Experience in UVM environment development for complex SoC or mixed-signal verification.
• Knowledge of both Synopsys and Cadence EDA tools.
• Exposure to behavioral modeling for analog/digital co-simulation.
• Experience with coverage-driven verification and automation frameworks.
• Excellent debugging analytical and problem-solving skills.
• Strong communication and teamwork abilities in a collaborative environment.

Additional Information

• On-site role in Austin TX (mandatory 5 days per week).
• Candidates must demonstrate stability in their career (no frequent job changes).
• H1-B sponsorship available for qualified candidates.

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