Silicon Physical Design Engineer III

Mackin Talent

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profile Job Location:

Charlotte, VT - USA

profile Monthly Salary: USD 198000 - 219000
profile Experience Required: 5years
Posted on: 30+ days ago
Vacancies: 1 Vacancy

Job Summary

This is a remote position.

Top non-negotiable skill sets required for this role:
Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
Experience with low power implementation power gating multiple voltage rails strong UPF/CPF knowledge.
Experience working with most EDA tools like DC/Genus ICC2/Innovus Primetime PTPX Primepower
Duties:
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis design for testability floorplan place and route static timing analysis IR Drop EM and physical verification in advanced technology nodes.
Resolve design and flow issues related to physical design identify potential solutions and drive execution
Power analysis based on netlist

Requirements

Must Have:
5 years of relevant physical design experience
Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts defining timing constraints and exceptions corners/voltage definitions.
Experience in chip power analysis
Experience with custom or regular clock tree synthesis implementation at block level or top level and clock power reduction techniques.
Experience with Python TCL Perl programming

Benefits

Mackin Talent offers an attractive benefits package which includes major medical carrier 15 days of PTO plus Holiday and Sick pay paid volunteer hours paternity/maternity leave and many more. We pride ourselves on our company values the top one being that Relationships Matter. Come experience the Mackin Difference and our welcoming company culture with a focus on teamwork and family. Learn more about Mackin and apply online at .


Required Skills:

Must Have: 5 years of relevant physical design experience Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs Knowledge of static timing analysis and concepts defining timing constraints and exceptions corners/voltage definitions. Experience in chip power analysis Experience with custom or regular clock tree synthesis implementation at block level or top level and clock power reduction techniques. Experience with Python TCL Perl programming


Required Education:

Education Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science Masters Degree preferred but not required

This is a remote position. Top non-negotiable skill sets required for this role: Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies Experience with low power implementation power gating multiple voltage rails strong UPF/CPF knowledge. ...
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IT Services and IT Consulting

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