DTCO Egineer

Responsibility:

for DTCO (Design-Technology Co-Optimization) for advanced process nodes working with Fab design and product teams to define technology identify optimization directions improve process and enhance PPA (Power Performance Area).
and optimize process knobs identify process/design risks and propose mitigation or optimization strategies.
on PPA targets define device types and specifications optimize standard cell/SRAM architectures and deliver corresponding DRM (Design Rule Manual) requirements.
process/design risks from OPC (Optical Proximity Correction) DFM (Design for Manufacturability) and DFR (Design for Reliability) perspectives and propose improvements.
on PPA analysis at module-level physical design propose SoC-level optimization strategies including physical design flow PDN (Power Delivery Network) design and metal stack definition.
benchmarking methodologies analyze and interpret PPA data.
research on industry DTCO trends and competitive analysis lead DTCO direction and define and optimize competitive process platforms.

Requirenment:

1. Technical Expertise Requirements: In-depth understanding of DTCO (Design-Technology Co-Optimization)
(1) Experience in process integration OPC DFM circuit design integrated circuit design FIP (e.g. standard cell and SRAM) design device and model definition DRM (Design Rule Manual) development etc.
(2) Familiar with semiconductor process flow or product development ground rules IC design circuit analysis layout RC extraction P&R (Place and Route) and other related knowledge.
(3) Proficient in Process Design Kits (PDKs) circuit design/simulation layout and Design Methodology tools with the ability to debug and solve technical issues.
(4) Knowledge of technology PPA (Power Performance Area) benchmarking.

2. Educational Requirements:
(1) Masters degree or above
(2) Majors in Microelectronics Electronics Electrical Engineering Materials Science Physics or related fields.

3. Work Experience:

510 years of relevant experience.