We are looking for candidates with a broad set of skills and interests especially in the SOC IO area. Candidates must have a strong curiosity and problem-solving mindset for technological innovations and challenges. Candidates will play a critical part in system validation optimization and integration of SoC IO interfaces from architecture concepts to final -to-day responsibility and tasks include the following electrical design review test bringup/debug and validation for various SOC low-speed/high-speed IO interfaces. Routine responsibilities also include factory build support and cross-team/cross-region collaboration.
Major in EE or equivalents BS MS or PhD. 3 years of equivalents experience.
Proven EE fundamentals knowledge in hardware system IO interfaces architecture.
Experience in signal integrity: modeling simulation and analysis
Hands on experience with lab equipment for high speed IO characterization and debug: Oscilloscope Spectrum Analyzer Logic Analyzer Power Supply DMM
Sufficient programming skill in Python/Lua.
Excellent written and verbal communication/presentation skills in English and Chinese.
Solid understanding of SOC technology and debug problems at various levels: from system circuit level to silicon transistor level
Solid understanding of design and validation requirements for low-speed and high-speed digital interfaces: I2C/SMBus SPI SPMI USB PCIe LPDP DisplayPort Clocks
Solid knowledge on SerDes and equalization
Experience in RF/IO Coex issue debug
Data analysis and visualization using Python Tableau JMP and/or Matlab
Beyond technical we honor curiosity creativity integrity leadership and collaboration
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