In this role you will: - Develop verification plans in coordination with design leads and architects.- Be responsible for planning building and maintaining verification test bench components and environments.- You will generate directed and constrained random tests. Run simulations and debug design and environment issues.- Create functional coverage points analyze coverage and improve test environment to target coverage holes.- Craft automated verification flows for block and chip level verification.- Apply knowledge of hardware description languages (VHDL/Verilog) hardware verification languages (SystemVerilog/UVM) and logic simulators to verify complex designs.- Work with other block and core level engineers to ensure a perfect verification flow.
Masters degree in Electrical Engineering Embedded Systems Computer Science or related field
Excellent communication and interpersonal skills combined with the ability to collaborate
Fluency in English
Deep knowledge of SystemVerilog and UVM
Experience developing scalable and portable test-benches
Experience with constrained random verification environments
Experience defining coverage space writing coverage model analyzing results
Experience with Assertion Based Verification
Experience in Formal Verification (Formal Linting Formal connectivity user property verification) is a plus
Experience with Python Perl or TCL
Understanding of AI and ML and their potential application to verification
Apple is an equal opportunity employer that is committed to inclusion and diversity
We take affirmative action to ensure equal opportunity for all applicants without regard to race color religion sex sexual orientation gender identity national origin disability Veteran status or other legally protected characteristics
Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities
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