Verification Engineer
Verification Engineer
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Job Description
Cambridge UK Full-time or Part-time Permanent Hybrid
Salary: 55000 to 68000 DOE
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlanes mission is to make quantum computing useful sooner. From advances in material science to complex chemistry simulation for drug design and discovery quantum computers will help solve some of the worlds most important challenges. Riverlane is building the quantum error correction stack Deltaflow to make this happen. Its a complex problem that requires a range of skills talent and passion.
We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC) and are partnering with many of the worlds leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. Were making remarkable progress and growing fast.
About the role
You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified trusted and performant solution. With full visibility of the entire stack you will own everything verification related. As a Senior Verification Engineer at Riverlane you will:
- Proactively work with designers and architects to define verification plans based on design specifications. You will own define and track detailed test plans for different blocks and system level.
- Implement scalable testbenches including checkers reference models and coverage groups in SystemVerilog. You will implement self-testing directed and random tests.
- Maintain the design verification environment keeping track of regression coverage metrics and bugs.
You do not need a background in quantum computing! You will learn this along the way.
Requirements
What we need
- Demonstrable commercial experience in functional verification including ownership of verification planning and strategy.
- A proactive and collaborative person who actively shares feedback and can independently define the scope of work.
- Proven experience of testbench design with verification frameworks like UVM/OVM.
- Knowledge of SystemVerilog assertion (SVA).
- Exposure to different programming languages such as C C and Python.
Even better if
- You have formal verification experience.
Benefits
What can you expect from us
- A comprehensive benefits package that includes an annual bonus plan private medical insurance life insurance and a contributory pension scheme
- Equity so that our team can share in the long-term success of Riverlane
- 28 days annual leave plus bank holidays and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development quantum information theory physics and maths) and over 20 different nationalities
- A learning environment that encourages individual team and company growth and learning including an annual training and conference budget for each staff member
Employment Type
Full Time
