Senior Staff Digital IC Designer
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Job Location:
Monthly Salary:
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Marvells high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem providing low-power high-performance solutions for cloud data center infrastructure service providers AI networks enterprises and 5G.This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies familiar names to all candidates.
You will be part of a highly-skilled dynamic team driving the development of Marvells next-generation high-speed PAM/Coherent DSPs and PHY designs which utilize cutting-edge CMOS technology.
As a member of a digital design team you will be assisting in chip design working closely with architecture team verification team supporting back-end teams and timing closure.
What You Can Expect
What You Can Expect
- Develop overall efficient RTL using (System)Verilog synthesis and backend resources.
- Integrate internal and external vendor IPs.
- Design debug and support ICs IPs and block DFT
- Implement and contribute specifying chip digital features.
- Work closely with the architecture floorplanning backend verification DFT STA teams and other cross functional teams to produce high quality hardware.
- Participate in various aspects of chip design RTL development DFT design synthesis static timing analysis formal equivalence RTL lint cross clock domain (CDC) analysis and functional verification.
- Develop ASIC specification and micro-architecture of signal processing and communications algorithms.
- Assist in design automation of various aspects of the CAD EDA flow.
- Develop post-silicon debug and correlation.
- Collaborate with cross-functional teams consisting of architects designers verification physical design and software/firmware engineers.
What Were Looking For
What Were Looking For:
- Candidate must have a MS/PhD (preferred) degree in EE or related technical field(s).
- Fluent in RTL coding design techniques. Experience DFT resets LEC Lint etc
- Experience working with multi-clock designs.
- Experience on synthesis static-timing closure formal verification gate-level simulations and block-level functional verification.
- Experience on Test structures for DFT IP Integration Fault models coverage improvement techniques.
- Hands-on experience on most aspects of chip-development process with proficiency in front-end design tools and methodologies.
- Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
- Must be a team player with a strong can-do attitude.
- Effective communication and presentation skills.
- Design experience in high speed (>1 GHz)/high-performance DSP products is highly desirable.
- Knowledge of scripting languages such as Python Perl Tcl and UNIX shell is highly desirable.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.
#LI-TT1Required Experience:
Staff IC
Key Skills
- Graphic Design
- CSS
- HTML5
- Adobe Creative Suite
- Fpga
- Digital design
- Web Design
- Adobe Photoshop
- Adobe Illustrator
- Responsive Web Design
- Sketch
- Adobe Indesign
About Company
Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
