ASIC Design Engineer
ASIC Design Engineer
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1 Vacancy
Job Description
Job Title: ASIC Design Engineer
Location: San Jose CA (Onsite from Day 1)
Job Description:
- Work as a member of the design team overseeing full-chip STA/SDCs and collaborate with Physical Design and DFT teams to close full-chip timing in multiple timing modes.
- Option to contribute to block-level RTL design or block/top-level IP integration.
- Develop efficient methodologies to promote block-level SDCs to full-chip and incorporate full-chip SDC changes back to block level.
- Ensure correctness and quality of SDCs early in the design cycle.
- Review block-level SDCs and clocking diagrams; mentor RTL design owners on SDC development.
- Create full-chip clocking diagrams and related documentation.
Minimum Qualifications:
- Bachelors in Electrical/Computer Engineering 7 years ASIC experience OR Masters 5 years ASIC experience.
- Hands-on experience with block/full chip SDC development in both functional and test modes.
- Strong experience with Static Timing Analysis (STA) using tools like PrimeTime/Tempus.
- Solid understanding of digital design concepts (clocking async boundaries).
- Experience with synthesis tools (Synopsys DC/DCG/FC) Verilog/System Verilog.
Preferred Qualifications:
- Experience with constraint analyzer tools (Synopsys TCM Cadence CCD).
- Knowledge of Spyglass CDC and glitch analysis.
- Familiarity with Formal Verification tools (Synopsys Formality Cadence LEC).
- Strong scripting skills in Python Perl or TCL.
Employment Type
Full-time
