Senior Layout Design Engineer (Analog/RF)
Senior Layout Design Engineer (Analog/RF)
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Job Description
Job Title: Senior Layout Design Engineer (Analog/RF)
Budget: 10 15 LPA
Location: Bangalore
Experience: 8 10 years
Role Overview:
We are hiring an experienced Senior Layout Engineer specializing in Analog/RF to take ownership of IC mask layout design physical verification and team leadership. You will work closely with circuit designers and CAD engineers to deliver high-quality mixed-signal semiconductor products.
Key Responsibilities:
- Perform IC mask layout and physical verification (LVS/DRC/antenna checks) for Analog/RF mixed-signal IO and ESD designs.
- Collaborate on custom analog mixed-signal layout planning and optimization.
- Ensure adherence to layout methodologies and flow standards.
- Lead a team of 4 5 layout engineers; contribute hands-on when needed.
- Resolve layout issues related to circuit reliability performance and manufacturability.
- Focus on higher technology nodes like 28nm/40nm and above. (Lower nodes like 3nm/4nm are not applicable.)
Required Skills and Experience:
- in Electronics or related discipline with 8 10 years in Analog/RF layout.
- Strong proficiency with Cadence Virtuoso (XL L) Mentor Calibre Assura/PVS and Linux OS.
- Expertise in transistor-level floor planning DRC/LVS/antenna/RC extraction.
- Hands-on knowledge of CMOS fabrication ESD latch-up RC delay and electromigration.
- Scripting knowledge in Skill Perl C-shell or TCL for automation.
- Excellent communication and documentation skills.
physical verification,analog semi conductors,cmos fabrication,communication,rc delay,mentor calibre,layout,linux os,circuit,esd control,design,cadence virtuoso,layout versus schematic (lvs),assura/pvs,tcl scripting,documentation,ic mask layout design,drc,latch-up,c-shell scripting,design rule checking (drc),drc/lvs/antenna/rc extraction,lvs,esd,skill scripting,perl scripting,transistor-level floor planning,team leadership,io,electromigration
Employment Type
Full Time
