Digital Layout Design Engineer
Digital Layout Design Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- BS and a minimum of 3 years relevant industry experience or equivalent years of experience
- We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits.
- High level proficiency in layout floorplanning standard cell planning and hierarchical layout assembly.
- Good understanding of issues with RC delay electromigration self heating and cross capacitance.
- Recognize failure prone layout structures dedicatedly work with designers for the best approach to problems.
- Excellent communication skills and able to work with multi-functional teams.
- Great skills on interpretation of CALIBRE DRC ERC LVS etc. reports.
- Knowledge of MENTOR GRAPHICS or CADENCE layout tools
- Scripting skills in CSH PERL or SKILL are considered a plus but not required.
- Experience in layout automation is considered a plus but not required.
- Experience in memory compiler development is considered a plus but not required.
- Experience designing low noise low power datapaths or Memory layout structures etc.
Employment Type
Full Time
