IP Design Engineer
IP Design Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Soft IP Development for FPGAs using Verilog/Systemverilog.
- Integrate third party IP cores into an FPGA system create custom RTL wrappers for third party cores and interface with IP vendors
- Work with Verification Engineers to verify IP and debug issues.
- Participate in board bring up as well as system level integration.
- 7 to 12 years of experience in digital design
- RTL coding experience using Verilog and/or System Verilog
- Strong in digital design micro architecture RTL development
- Working experience of the Xilinx FPGA and Vivado
- Experience in Video domain (DisplayPort/MIPI/HDMI/SDI) is preferred
- Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs/Solutions
- Good understanding of system design aspects and its impact on performance and throughput
Employment Type
Full-time
