Work with CPU CAD and design teams to engineer new flows/algorithms to improve PPA Detailed analysis across partitions to understand optimization opportunity Develop new PD focused flows to improve CPU performance and efficiency Cross-functional collaboration across STA library tech and post silicon team to improve optimization during physical design
Minimum BS and 10 years of relevant industry experience
Electrical engineering fundamentals in digital circuits timing/power concepts and logic design
Scripting skills to interface with tools and mine data
Strong fundamentals in high-performance & low-power physical design techniques
Experience in using industry-standard synthesis PnR and STA tools
Proficiency in programming and scripting in Python TCL or Perl
Understanding of challenges related to latest deep sub-micron technology and ability to write algorithms and code to extract Power Performance & Area during physical design
Ability to work independently and/or lead physical design methodology and optimization techniques across partitions in collaboration with x-functional teams
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