In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence linting and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams.
Bachelors degree with minimum 3 years of relevant experience
Excellent knowledge of SystemVerilog and Assertions
Ability to read custom circuit schematics and understand functionality
Solid understanding of logic/SPICE simulations as well as SPICE/HDL co-simulations
Excellent knowledge of digital logic gates clocking and state elements
Basics of passive and active circuit elements voltage and current sources and analog blocks like amplifiers ADCs/DACs/Comparators
Familiarity of writing scripts in PERL/Python is a strong plus
Familiarity with formal equivalence and Lint/CDC/RDC tools is a strong plus
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