drjobs Graphics FE Implementation Engineer

Graphics FE Implementation Engineer

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1 Vacancy
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Job Location drjobs

Austin - USA

Monthly Salary drjobs

Not Disclosed

drjobs

Salary Not Disclosed

Vacancy

1 Vacancy

Job Description

Candidates will be responsible for PPA optimization of the netlist working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration you will deliver the best-in-class GPUs for the best consumer products. If youre ready to help chart the future of Apple Silicon wed love to talk to you.


  • Experience with physical synthesis including logic and PPA optimization techniques
  • Experience with Verilog System Verilog or other scripting languages
  • Experience using logic equivalence tools for RTL and Gate-level designs
  • BS 3 years of relevant experience


  • Understanding and application of physical design (PD) and static timing analysis (STA) principles
  • Ability to analyze critical paths and guide RTL designs to optimal solutions
  • Collaborate effectively with IP teams spanning multiple sites
  • Familiarity with DFT insertion
  • Familiarity with reset domain multi-clock domain multi-power domain (UPF) linting tools and concepts across RTL and Gate-Level
  • Experience implementing ECOs for functionality and timing

Employment Type

Full-Time

Company Industry

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