RTL Design Engineer
RTL Design Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- BS degree in technical discipline with minimum 3 years of proven experience.
- Solid understanding of mixed signal concepts RTL design Verilog and SystemVerilog.
- Good fundamental knowledge of front-end tools and methodologies (Verilog simulators linters clock-domain crossing reset domain crossing unified power flow logic equivalence checkers).
- Validated knowledge of synthesis static timing DFT is a plus.
- Validated knowledge of SystemVerilog assertions checkers and other design verification techniques are a plus.
- Knowledge of scripting languages. Perl and Python are plusses.
- Strong communication and presentation skills.
Employment Type
Full Time
