CPU Cache Microarchitect/RTL Engineer
CPU Cache Microarchitect/RTL Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Minimum BS and 3 years of relevant industry experience
- Experience with microprocessor cache design or coherent system cache design
- Experience with Verilog and/or VHDL
- Knowledge of microprocessor architecture
- Experience with simulators and waveform debugging tools
- Expertise in one or more of the following areas: Coherence protocols and interconnects high performance (low latency high bandwidth) design techniques or memory subsystem queuing scheduling; starvation and deadlock avoidance
- SRAM design basics
- Multiple clock/power domains and power management strategies
- Prefetchers replacement policies
- Debug capabilities
- DFT strategies
- Error detection and correction
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C programming
- Experience using an interpretive language such as Perl or Python
Employment Type
Full Time
