In this role you will: - Develop verification plans in coordination with design leads and architects.- Build and maintain portable verification test bench components and environments.- Generate directed and constrained random tests.- Run simulations and debug design and environment issues.- Create functional coverage points analyze coverage and improve test environment to target coverage holes.- Create automated verification flows for block verification.- Apply knowledge of hardware description languages (VHDL/Verilog) to verify complex designs.- Work with other block subsystem and chip level engineers to ensure seamless verification flow.
Previous design verification experience required.
Experience developing unit or cluster level test environments.
BS 10 years of relevant experience.
Experience with verification languages such as SystemVerilog.
Experience with HDL simulators and waveform viewers.
Experience in cache or memory hierarchy verification is a strong plus.
Experience with GPU unit testing highly desired.
Understanding of the Graphics Pipeline a plus.
Experience defining and executing unit level test plans.
Experience with common verification methodologies such as UVM.
Experience defining coverage space writing coverage and coverage closure.
Solid fundamental software and programming skills.
Experience with Perl Ruby Shell scripting Makefiles.
Disclaimer: Drjobpro.com is only a platform that connects job seekers and employers. Applicants are advised to conduct their own independent research into the credentials of the prospective employer.We always make certain that our clients do not endorse any request for money payments, thus we advise against sharing any personal or bank-related information with any third party. If you suspect fraud or malpractice, please contact us via contact us page.