Responsibilities include especially but are not limited to:Reviewing Architecture and Design attributes and verification test benches generating directed/constrained random test simulations debugging failures tracking bugs and closing schedules and supporting multi-functional engineering in verification flows automation scripts and with test engineers to bring up test patterns on silicon.
/ in Electrical or Computer Engineering.
Shown understanding and experience in directed or random verification coverage analysis and assertions.
Good knowledge of general logic design principles.
Ability to fluently speak and write in English.
Proficient in a scripting language such as Python TCL or Perl.
Excellent skills in problem-solving communication.
Exposure to OOP programming using HDLs/HVLs such at System Verilog or C/C.
Exposure to any aspect of DFT is a plus.
Experience in large SoC design or verification - would be a plus.
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