Senior Verification Engineer
Senior Verification Engineer
Posted on :
02-08-2025
Employer Active
1 Vacancy
Job Alert
You will be updated with latest job alerts via emailValid email field required
Send jobs
Share
Send me jobs like this
Job Alert
You will be updated with latest job alerts via emailValid email field required
Send jobs
Job Description
Requirements
- 6 years of experience a must
- Performed at last 2 or more full block/system verification cycles.
- In depth knowledge in VLSI verification flow languages and concepts.
- Experience in data path or data protocols specifically Ethernet - preferred
- Verification using one of the known methodologies (eRM UVM OVM).
Responsibilities
- Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
- Build verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for corner-cases.
- Debug the functionality with design engineers.
- Perform coverage collection and follow the metrices to close the full functionality.
Required Citizenship / Work Permit / Visa Status
Will sponsor H1-B
Must-Haves
-On-site in Austin TX five days a week.
-Performed at least 2 or more full block/system verification cycles.
-In depth knowledge in VLSI verification flow languages and concepts.
Employment Type
Full Time
Key Skills
Report This Job
Disclaimer: Drjobpro.com is only a platform that connects job seekers and employers. Applicants are advised to conduct their own independent research into the credentials of the prospective employer.We always make certain that our clients do not endorse any request for money payments, thus we advise against sharing any personal or bank-related information with any third party. If you suspect fraud or malpractice, please contact us via contact us page.
