Ownership of SerDes system bring-up validation and debug. This will involve a SerDes bring up in system environment verifying basic operations analyzing robustness and margins in system. Work with design teams to understand the architecture and define DFT needs to help improve testability and first time silicon success. Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.
Bachelors Degree in a technical area plus 7 years of experience.
The ideal candidate should have experience in high-speed serial links with expertise in the following:
Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g. PCIe USB SATA etc.)
Deep knowledge in system bring-up of high-speed serial links lab testing and defining equipment needs
Strong knowledge in scripting (e.g. python C Matlab) for automation of validation efforts. Experience with system level S/W setup is a plus
Knowledge of SerDes design and architecture including CDR and equalization
Able to think outside the box and come with creative solutions for system validation.
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